Reduced scaling or shrinking of the geometries of devices used in integrated semiconductor circuit technology for forming denser circuits has required voltage supply sources to provide lower voltages than the heretofore generally accepted standard supply voltage of 5 volts, particularly in order to avoid a voltage breakdown in the insulation layers. During the transition from 5 volt supplies to the lower voltage supplies of, say, 3.3 volts, a mix of circuits is being used wherein some of the circuits have been designed for use with standard 5 volt supplies while other circuits have been designed for use with the lower 3.3 volt supplies. In general, the geometries of memory circuits are reduced at a faster rate than are the geometries of logic circuits which are coupled to the memory circuits. Accordingly, a voltage mismatch results during this transition period when multiple levels of power supplies coexist in a given system.
In U.S. Pat. No. 4,469,959, filed by K. Luke et al on Mar. 15, 1982, there is disclosed a circuit for controlling the supply voltage to a complementary metal oxide semiconductor (CMOS) inverter circuit which uses first and second voltage sources wherein a voltage magnitude variation in the first supply source causes the second supply source to be connected to the inverter circuit.
U.S. Pat. No. 3,076,135, filed by R. P. Farnsworth et al on Sept. 29, 1958, discloses a transistor power supply system which turns off under an overload condition and turns on upon the removal of the overload.
U.S. Pat. No. 4,309,627, filed by J. Tabata on Mar. 27, 1979, discloses a detecting circuit for a power source voltage which includes a reference voltage generating circuit, a voltage dividing circuit and a voltage comparing circuit.
U.S. Pat. No. 4,463,270, filed by J. S. Gordon on July 24, 1980, discloses a comparator circuit for detecting a difference in relative magnitudes of two voltages which is suitable for controlling a battery backup power supply.